CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 370

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.20.15
370
PLMBASE_REG - Protected Low Memory Base Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to set up the base address of DMA-protected low-memory region below 4 GB.
This register must be set up before enabling protected memory through PMEN_REG,
and must not be updated when protected memory regions are enabled.
When the LT CMD.LOCK.PMRC command is invoked, this register is locked (treated as
RO). When the LT CMD.UNLOCK.PMRC command is invoked, this register is unlocked
(treated as RW).
This register is always treated as RO for implementations not supporting protected low
memory region (PLMR field reported as 0 in the Capability register).
The alignment of the protected low memory region base depends on the number of
reserved bits (N:0) of this register. Software may determine N by writing all 1s to this
register, and finding the most significant bit position with 0 in the value read back from
the register. Bits N:0 of this register are decoded by hardware as all 0s.
Software must setup the protected low memory region below 4 GB.
31:21
20:0
Bit
Bit
0
Access
Access
RW
RO
RO
000000h
Default
Default
Value
000h
Value
0b
Protected Low-Memory Base (PLMB)
This register specifies the base of protected low-memory
region in system memory.
Reserved
Protected Region Status (PRS)
This field indicates the status of protected memory
region(s)
0 = Protected memory region(s) disabled.
1 = Protected memory region(s) enabled.
0/2/0/GFXVTBAR
68-6Bh
00000000h
RO; RW
32 bits
(Sheet 2 of 2)
Processor Configuration Registers
Description
Description
Datasheet