CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 12

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1
1.1
12
Processor Configuration
Registers
This is volume 2 of the Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile Processor
Series Datasheet. Throughout this document, the Intel Core i7-600, i5-500, i5-400 and
i3-300 Mobile Processor Series may be referred to as simply the processor. This
document provides register information for the processor.
Register Terminology
The following table shows the register-related terminology that is used in this
document.
RO
RO-V
RO-V-S
AF
RW
RW1C
Item
Read Only bit(s). Writes to these bits have no effect. These are static values
only.
Read Only/Volatile bit(s). Writes to these bits have no effect. These are
status bits only. The value to be read may change based on internal events.
Read Only/Volatile/Sticky bit(s). Writes to these bits have no effect.
These are status bits only. The value to be read may change based on internal
events. Bits are not returned to their default values by “warm” reset, but is
reset with a cold/complete reset (for PCI Express* related bits a cold reset is
“Power Good Reset” as defined in the PCI Express Base Specification).
Atomic Flag bit(s). The first time the bit is read with an enabled byte, it
returns the value 0, but a side-effect of the read is that the value changes to
1. Any subsequent reads with enabled bytes return a 1 until a 1 is written to
the bit. When the bit is read, but the byte is not enabled, the state of the bit
does not change, and the value returned is irrelevant, but will match the state
of the bit.
When a 0 is written to the bit, there is no effect. When a 1 is written to the bit,
its value becomes 0, until the next byte-enabled read. When the bit is written,
but the byte is not enabled, there is no effect.
Conceptually, this is “Read to Set, Write 1 to Clear”
Read/Write bit(s). These bits can be read and written by software.
Hardware may only change the state of this bit by reset.
Read/Write 1 to Clear bit(s). These bits can be read. Internal events may
set this bit. A software write of 1 clears (sets to 0) the corresponding bit(s)
and a write of 0 has no effect.
(Sheet 1 of 3)
Description
Processor Configuration Registers
Datasheet