CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 72

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

72
These bits are Intel TXT lockable.
15:4
3:0
Bit
According to the above equation, TOLUD is originally calculated to: 4 GB =
1_0000_0000h
The system memory requirements are: 4 GB (max addressable space) – 1 GB (PCI
space) – 35 MB (lost memory) = 3 GB – 35 MB (minimum granularity) =
0_ECB0_0000h
Since 0_ECB0_0000h (PCI and other system requirements) is less than
1_0000_0000h, TOLUD should be programmed to ECBh.
Access
RW-L
RO
Default
0000b
Value
001h
Top of Low Usable DRAM (TOLUD)
This register contains Bits 31:20 of an address one byte
above the maximum DRAM memory below 4 GB that is
usable by the operating system. Address Bits 31 down to 20
programmed to 01h implies a minimum memory size of 1
MB.
Configuration software must set this value to the smaller of
the following two choices: Maximum amount memory in the
system minus Intel ME stolen memory plus one byte or the
minimum address allocated for PCI memory.
Address Bits 19:0 are assumed to be 0_0000h for the
purposes of address comparison. The Host interface
positively decodes an address towards DRAM if the incoming
address is less than the value programmed in this register.
The Top of Low Usable DRAM is the lowest address above
both Graphics Stolen memory and TSEG. BIOS determines
the base of Graphics Stolen Memory by subtracting the
Graphics Stolen Memory Size from TOLUD and further
decrements by TSEG size to determine base of TSEG. All the
Bits in this register are locked in Intel VT-d mode.
This register must be 64-MB aligned when reclaim is
enabled.
Reserved
Processor Configuration Registers
Description
Datasheet