CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 231

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.16.9
1.16.10
Datasheet
HDR2 - Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register contains the Header Type of the IGD.
GTTMMADR - Graphics Translation Table, Memory Mapped
Range Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register requests allocation for the combined Graphics Translation Table
Modification Range and Memory Mapped Range. The range requires 4 MB combined for
MMIO and Global GTT aperture, with 512K of that used by MMIO and 2 MB used by GTT.
GTTADR will begin at (GTTMMADR + 2 MB) while the MMIO base address is the same as
GTTMMADR.
For the Global GTT, this range is defined as a memory BAR in graphics device config
space. It is an alias into which software is required to write Page Table Entry values
(PTEs). Software may read PTE values from the global Graphics Translation Table
(GTT). PTEs cannot be written directly into the global GTT memory area.
The device snoops writes to this region in order to invalidate any cached translations
within the various TLB's implemented on-chip. There are some exceptions to this - see
GTT-TLB in the Programming Interface chapter.
The allocation is for 4 MB and the base address is defined by bits [35:22].
6:0
Bit
7
Access
RO
RO
Default
Value
00h
0b
Multi Function Status (MFUNC)
Indicates if the device is a Multi-Function Device. The value is
hard wired to 0 to indicate that this Internal Graphics Device
is a single-function device.
Header Code (H)
This is a 7-bit value that indicates the Header Code for the
IGD. This code has the value 00h, indicating a type 0
configuration space format.
0/2/0/PCI
Eh
00h
RO
8 bits
0/2/0/PCI
10-17h
0000000000000004h
RO; RW
64 bits
Description
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