CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 80

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.9.1
80
CSZMAP - Channel Size Mapping
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
This register indicates the total memory which is mapped to Interleaved and Asymmetric
operation respectively (1MB granularity) used for Channel address decode.
63:48
47:32
31:16
15:0
Bit
Access
RW-L
RW-L
RW-L
RO
Default
Value
0000h
0000h
0000h
0h
Reserved
2 Channel Size (2CHSZ)
This register indicates the total memory which is mapped to
2-channel operation (1-MB granularity)
This register is locked by Intel ME stolen Memory lock and
may also be forced to 0000h by the Performance Dual
Channel Disable fuse.
1 Channel Size (1CHSZ)
This register indicates the total memory which is mapped to
1-channel operation (1-MB granularity)
This register is locked by Intel ME stolen Memory lock.
Channel 0 Single Channel Size (C0SCSIZE)
This register indicates the quantity of memory physically in
channel 0 which is mapped to 1-channel operation (1-MB
granularity).
0/0/0/MCHBAR
100-107h
0000000000000000h
64 bits
0000h
RW-L
Processor Configuration Registers
Description
Datasheet