CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 88

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.9.9
88
C0CYCTRKPCHG - Channel 0 CYCTRK PCHG
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 0 CYCTRK Precharge Registers.
15:11
10:6
5:2
1:0
Bit
Access
RW
RW
RW
RO
Default
Value
00h
00h
00b
0h
Reserved
Write To Precharge Delay (C0sd_cr_wr_pchg)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the WRITE and PRE
commands to the same rank-bank.
Corresponds to the tWR parameter in the DDR3
Specification.
Read To Precharge Delay (C0sd_cr_rd_pchg)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the READ and PRE
commands to the same rank-bank.
Precharge To Precharge Delay (C0sd_cr_pchg_pchg)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two PRE commands to
the same rank.
0/0/0/MCHBAR
250-251h
0000h
RO; RW
16 bits
Processor Configuration Registers
Description
Datasheet