CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 127

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.10.11
Datasheet
TERRCMD - Thermal Error Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register select which errors are generate a SERR DMI interface special cycle, as
enabled by ERRCMD [SERR Thermal Sensor event]. The SERR and SCI must not be
enabled at the same time for the thermal sensor event.
7:6
Bit
5
4
3
2
1
0
Access
RW
RW
RW
RW
RW
RW
RO
Default
Value
00b
0b
0b
0b
0b
0b
0b
Reserved
SERR on Catastrophic Thermal Sensor Event
(CATSERR)
0 = Disable. Reporting of this condition via SERR messaging
1 = Does not mask the generation of a SERR DMI cycle on a
SERR on Hot Thermal Sensor Event (HOTSERR)
0 = Disable. Reporting of this condition via SERR messaging
1 = Do not mask the generation of a SERR DMI cycle on a
SERR on Aux 3 Thermal Sensor Event (AUX3SERR)
0 = Disable. Reporting of this condition via SERR messaging
1 = Do not mask the generation of a SERR DMI cycle on an
SERR on Aux 2 Thermal Sensor Event (AUX2SERR)
0 = Disable. Reporting of this condition via SERR messaging
1 = Do not mask the generation of a SERR DMI cycle on an
SERR on Aux 1 Thermal Sensor Event (AUX1SERR)
0 = Disable. Reporting of this condition via SERR messaging
1 = Do not mask the generation of a SERR DMI cycle on an
SERR on Aux 0 Thermal Sensor Event (AUX0SERR)
0 = Disable. Reporting of this condition via SERR messaging
1 = Do not mask the generation of a SERR DMI cycle on an
0/0/0/MCHBAR
10E4h
00h
RO; RW
8 bits
is disabled.
catastrophic thermal sensor trip.
is disabled.
Hot thermal sensor trip.
is disabled.
Aux3 thermal sensor trip.
is disabled.
Aux2 thermal sensor trip.
is disabled.
Aux1 thermal sensor trip.
is disabled.
Aux0 thermal sensor trip.
Description
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