CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 292

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

292
47:32
31:0
Bit
49
48
Access
RW
RW
RW
RO
00000000h
000000h
Default
Value
0000h
00h
Drain Reads (DR)
This field is ignored by hardware if the DRD field is
reported as clear in the Capability register. When DRD
field is reported as set in the Capability register, the
following encodings are supported for this field:
0 = Hardware may complete the IOTLB invalidation
1 = Hardware must drain all/relevant translated DMA
Drain Writes (DW)
This field is ignored by hardware if the DWD field is
reported as clear in the Capability register. When DWD
field is reported as set in the Capability register, the
following encodings are supported for this field:
0 = Hardware may complete the IOTLB invalidation
1 = Hardware must drain all/relevant translated DMA
Domain-ID (DID)
Indicates the id of the domain whose IOTLB entries needs
to be selectively invalidated. This field must be
programmed by software for domain-selective, domain
page-selective and device-page-selective invalidation
requests.
The Capability register reports the domain-id width
supported by hardware. Software must ensure that the
value written to this field is within this limit.
Hardware may ignore and not implement Bits 47:(32+N)
where N is the supported domain-id width reported in the
capability register.
Reserved
(Sheet 3 of 3)
without draining any translated DMA reads that are
queued in the root-complex and yet to be processed.
reads that are queued in the root-complex before
indicating IOTLB invalidation completion to software.
A DMA read request to system memory is defined as
drained when root-complex has finished fetching all of
its read response data from memory.
without draining any translated DMA writes that are
queued in the root-complex for processing.
writes that are queued in the root-complex before
indicating IOTLB invalidation completion to software.
A DMA write request to system memory is defined as
drained when the effects of the write is visible to
processor accesses to all addresses targeted by the
DMA write.
Processor Configuration Registers
Description
Datasheet