CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 376

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.20.22
1.20.23
376
ICS_REG - Invalidation Completion Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to report completion status of invalidation wait descriptor with Interrupt Flag
(IF) Set. This register is treated as RsvdZ by implementations reporting Queued
Invalidation (QI) as not supported in the Extended Capability register.
IECTL_REG - Invalidation Completion Event Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the invalidation event interrupt control bits. This register is treated
as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in
the Extended Capability register.
31:1
Bit
Bit
31
0
Access
Access
RO
RO
RO
00000000h Reserved
Default
Default
Value
Value
0b
1b
Invalidation Wait Descriptor Complete (IWC)
Indicates completion of Invalidation Wait Descriptor with
Interrupt Flag (IF) field Set.
Hardware implementations not supporting queued
invalidations implement this field as RsvdZ.
Interrupt Mask (IM)
0 = No masking of interrupt. When a invalidation event
1 = This is the value on reset. Software may mask
0/2/0/GFXVTBAR
9C-9Fh
00000000h
RO
32 bits
0/2/0/GFXVTBAR
A0-A3h
80000000h
RO
32 bits
(Sheet 1 of 2)
condition is detected, hardware issues an interrupt
message (using the Invalidation Event Data &
Invalidation Event Address register values).
interrupt message generation by setting this field.
Hardware is prohibited from sending the interrupt
message when this field is Set.
Processor Configuration Registers
Description
Description
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