CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 65

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
Bit
0
Access
RW
Default
Value
0b
This bit works with the VGA Enable bits in the BCTRL
register of Device 1 to control the routing of CPU initiated
transactions targeting MDA compatible I/O and memory
address ranges. This bit should not be set if device 1's VGA
Enable bit is not set.
If Device 1's VGA enable bit is not set, then accesses to I/O
address range x3BCh-x3BFh remain on the backbone.
If the VGA enable bit is set and MDA is not present, then
accesses to IO address range x3BCh-x3BFh are forwarded to
PCI Express through device 1 if the address is within the
corresponding IOBASE and IOLIMIT, otherwise they remain
on the backbone.
MDA resources are defined as the following:
(including ISA address aliases, A[15:10] are not used in
decode)
Any I/O reference that includes the I/O locations listed
above, or their aliases, will remain on the backbone even if
the reference also includes I/O locations not listed above.
The following table shows the behavior for all combinations
of MDA and VGA:
VGA and MDA memory cycles can only be routed across
PEG0 when MAE (PCICMD1[1]) is set. VGA and MDA I/O
cycles can only be routed across PEG0 if IOAE (PCICMD1[0])
is set.
PEG0 MDA Present (MDAP0)
VGAEN
Encoding
Memory:0B0000h - 0B7FFFh
I/O:3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
0
0
1
1
(Sheet 2 of 2)
0b
1b
MDAP
0
1
0
1
All References to MDA and VGA space
are not claimed by Device 1
Illegal combination
All VGA and MDA references are
routed to an external graphics device
attached to PCI Express Device 1
All VGA references are routed to an
external graphics device attached to
PCI Express Device 1. MDA references
are not claimed by Device 1.
Description
Description
MDA Present
No MDA
Description
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