CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 254
CP80617004119AES LBU3
Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet
1.CP80617004119AES_LBU3.pdf
(388 pages)
Specifications of CP80617004119AES LBU3
Lead Free Status / RoHS Status
Compliant
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1.18.1
254
PEG VT-d
Completion
Resource
Dedication
DMA Remap Engine
Policy Control
Register Name
VER_REG - Version Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to report the architecture version supported. Backward compatibility for the
architecture is maintained with new revision numbers, allowing software to load DMA-
remapping drivers written for prior architecture versions.
31:8
7:4
3:0
Bit
PEGVTCMPLRESR
VTPOLICY
Register
Access
Symbol
RO
RO
RO
00000000
00000000
00000000
Default
Value
0001b
0000b
b
Register
Start
F08
FFC
(Sheet 3 of 3)
Reserved
Major Version number (MAX)
Indicates supported architecture version.
Minor Version number (MIN)
Indicates supported architecture minor version.
0/0/0/VC0PREMAP
0-3h
00000010h
RO
32 bits
Register End
F0B
FFF
Processor Configuration Registers
Description
Default Value
20004000h
00000000h
RW-L; RO
RW-L
Access
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