CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 9

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Datasheet
1.20
1.21
1.19.30FRCD_REG - Fault Recording Registers .................................................... 341
1.19.31VTPOLICY - DMA Remap Engine Policy Control.......................................... 342
GFXVTBAR...................................................................................................... 344
1.20.1 VER_REG - Version Register................................................................... 346
1.20.2 CAP_REG - Capability Register ............................................................... 346
1.20.3 ECAP_REG - Extended Capability Register ................................................ 351
1.20.4 GCMD_REG - Global Command Register .................................................. 353
1.20.5 GSTS_REG - Global Status Register ........................................................ 357
1.20.6 RTADDR_REG - Root-Entry Table Address Register.................................... 359
1.20.7 CCMD_REG - Context Command Register ................................................ 360
1.20.8 FSTS_REG - Fault Status Register........................................................... 363
1.20.9 FECTL_REG - Fault Event Control Register ............................................... 365
1.20.10FEDATA_REG - Fault Event Data Register ................................................ 367
1.20.11FEADDR_REG - Fault Event Address Register............................................ 367
1.20.12FEUADDR_REG - Fault Event Upper Address Register ................................ 368
1.20.13AFLOG_REG - Advanced Fault Log Register .............................................. 368
1.20.14PMEN_REG - Protected Memory Enable Register ....................................... 369
1.20.15PLMBASE_REG - Protected Low Memory Base Register .............................. 370
1.20.16PLMLIMIT_REG - Protected Low Memory Limit Register.............................. 371
1.20.17PHMBASE_REG - Protected High Memory Base Register ............................. 372
1.20.18PHMLIMIT_REG - Protected High Memory Limit Register ............................ 373
1.20.19IQH_REG - Invalidation Queue Head ....................................................... 374
1.20.20IQT_REG - Invalidation Queue Tail.......................................................... 374
1.20.21IQA_REG - Invalidation Queue Address ................................................... 375
1.20.22ICS_REG - Invalidation Completion Status ............................................... 376
1.20.23IECTL_REG - Invalidation Completion Event Control .................................. 376
1.20.24IEDATA_REG - Invalidation Completion Event Data ................................... 377
1.20.25IEADDR_REG - Invalidation Completion Event Address .............................. 378
1.20.26IEUADDR_REG - Invalidation Completion Event Upper Address ................... 378
1.20.27IRTA_REG - Interrupt Remapping Table Address....................................... 379
1.20.28IVA_REG - Invalidate Address Register .................................................... 380
1.20.29IOTLB_REG - IOTLB Invalidate Register ................................................... 382
1.20.30FRCD_REG - Fault Recording Registers .................................................... 384
Intel® Trusted Execution Technology (Intel® TXT) Specific Registers..................... 386
1.21.1 TXT.DID - TXT Device ID Register........................................................... 386
1.21.2 TXT.DPR - DMA Protected Range ............................................................ 387
1.21.3 TXT.PUBLIC.KEY.LOWER - TXT Processor Public Key Hash Lower Half .......... 388
1.21.4 TXT.PUBLIC.KEY.UPPER - TXT Processor Public Key Hash Upper Half ........... 388
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