CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 148

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.12.4
1.13
148
Vendor
Identification
Device
Identification
PCI Command
PCI Status
Warning:
Register Name
PMCFG - Power Management Configuration
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This Register bit field shall contain the default unless otherwise indicated in the BIOS
Specification.
PCI Device1
Device 1 contains the controls associated with the PCI Express x16 root port that is the
intended to attach as the point for external graphics. It is typically referred to as PCI
EXPRESS-G (PCI Express graphics) port. In addition, it also functions as the virtual PCI-
to-PCI bridge.
When reading the PCI Express “conceptual” registers such as this, you may not get a
valid value unless the register value is stable.
The PCI Express based specification defines two types of reserved bits.
Reserved and Preserved:
Unless explicitly documented as Reserved and Zero, all bits marked as reserved are
part of the Reserved and Preserved type, which have historically been the typical
definition for Reserved.
It is important to note that most (if not all) control bits in this device cannot be
modified unless the link is down. Software is required to first Disable the link, then
program the registers, and then re-enable the link (which will cause a full-retrain with
the new settings).
1. Reserved for future RW implementations; software must preserve value read for
2. Reserved and Zero: Reserved for future R/WC/S implementations; software must
writes to bits.
use 0 for writes to bits.
VID1
DID1
PCICMD1
PCISTS1
Register
Symbol
Register Start
6
0
2
4
(Sheet 1 of 3)
0/0/0/MCHBAR
1210h
04h
RW; RW-P
8 bits
Register End
1
3
5
7
Processor Configuration Registers
Default Value
8086h
0045h
0000h
0010h
RO; RWC
RO; RW
Access
RO
RO
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