CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 334

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.19.25
1.19.26
334
IEADDR_REG - Invalidation Event Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the Invalidation Event Interrupt message address. This register is
treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
IEUADDR_REG - Invalidation Event Upper Address
Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the Invalidation Event interrupt message upper address. This
register is treated as RsvdZ by implementations reporting both Queued Invalidation
(QI) and Extended Interrupt Mode (EIM) as not supported in the Extended Capability
register.
31:2
31:0
1:0
Bit
Bit
Access
Access
RO
RO
RO
00000000h Message Address (MA)
00000000h
Default
Default
Value
Value
00b
When fault events are enabled, the contents of this register
specify the DWORD-aligned address (Bits 31:2) for the
interrupt request.
Software requirements for programming this register are
described in Intel VT-d specification Section 5.7.
Reserved
Message Upper Address (MUA)
Hardware implementations supporting Queued
Invalidations and Extended Interrupt Mode are required to
implement this register.
Software requirements for programming this register are
described in Section 5.7. Hardware implementations not
supporting Queued Invalidations and Extended Interrupt
Mode may treat this field as RSVD.
0/0/0/DMIVC1REMAP
A8-ABh
00000000h
RO
32 bits
0/0/0/DMIVC1REMAP
AC-AFh
00000000h
RO
32 bits
Processor Configuration Registers
Description
Description
Datasheet