CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 185

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.13.39
Datasheet
LCTL - Link Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Allows control of PCI Express link.
15:12
Bit
11
10
9
8
Access
RW
RW
RW
RO
RO
Default
Value
0000b
0b
0b
0b
0b
Reserved
Link Autonomous Bandwidth Interrupt Enable (LABIE)
When Set, this bit enables the generation of an interrupt to
indicate that the Link Autonomous Bandwidth Status bit has
been Set.
This bit is not applicable and is reserved for Endpoint devices,
PCI Express to PCI/PCI-X bridges, and Upstream Ports of
Switches.
Devices that do not implement the Link Bandwidth
Notification capability must hardwire this bit to 0b.
Link Bandwidth Management Interrupt Enable (LBMIE)
When Set, this bit enables the generation of an interrupt to
indicate that the Link Bandwidth Management Status bit has
been Set.
This bit is not applicable and is reserved for Endpoint devices,
PCI Express to PCI/PCI-X bridges, and Upstream Ports of
Switches.
Hardware Autonomous Width Disable (HAWD)
When Set, this bit disables hardware from changing the Link
width for reasons other than attempting to correct unreliable
Link operation by reducing Link width.
Devices that do not implement the ability autonomously to
change Link width are permitted to hardwire this bit to 0b.
Enable Clock Power Management (ECPM)
Applicable only for form factors that support a “Clock
Request” (CLKREQ#) mechanism, this enable functions as
follows:
0b – Clock power management is disabled and device must
hold CLKREQ# signal low.
1b - When this bit is set to 1 the device is permitted to use
CLKREQ# signal to power manage link clock according to
protocol defined in appropriate form factor specification.
Default value of this field is 0b. Components that do not
support Clock Power Management (as indicated by a 0b value
in the Clock Power Management bit of the Link Capabilities
Register) must hardwire this bit to 0b.
0/1/0/PCI
B0-B1h
0000h
RO; RW; RW-SC
16 bits
(Sheet 1 of 3)
Description
185