CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 336

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.19.28
336
IVA_REG - Invalidate Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to provide the DMA address whose corresponding IOTLB entry needs to be
invalidated through the corresponding IOTLB Invalidate register. This register is a
write-only register. Value returned on reads of this register is undefined.
63:12
11:7
Bit
6
Access
RO
W
W
00000000
Default
00000h
Value
00h
0b
Address (ADDR)
Software provides the DMA address that needs to be page-
selectively invalidated. To request a page-selective
invalidation request to hardware, software must first write
the appropriate fields in this register, and then issue
appropriate page-selective invalidate command through the
IOTLB_REG.
Hardware ignores Bits 63:N, where N is the maximum guest
address width (MGAW) supported.
Value returned on read of this field is undefined.
Reserved
Invalidation Hint (IH)
The field provides hint to hardware to preserve or flush the
non-leaf (page-directory) entries that may be cached in
hardware.
0 = Software may have modified both leaf and non-leaf
1 = Software has not modified any non-leaf page-table
Value returned on read of this field is undefined.
0/0/0/DMIVC1REMAP
100-107h
0000000000000000h
W;RO
64 bits
page-table entries corresponding to mappings specified
in the ADDR and AM fields. On a page-selective
invalidation request, hardware must flush both the
cached leaf and non-leaf page-table entries
corresponding to mappings specified by ADDR and AM
fields.
entries corresponding to mappings specified in the
ADDR and AM fields. On a page-selective invalidation
request, hardware may preserve the cached non-leaf
page-table entries corresponding to mappings specified
by ADDR and AM fields.
(Sheet 1 of 2)
Processor Configuration Registers
Description
Datasheet