CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 14

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.2
14
Note:
System Address Map
The processor is a multi-chip package (MCP) and basically consists of the CPU and the
north bridge chipset, i.e., GMCH combined together in a single package. Hence this
section will make reference to CPU as well as GMCH address mapping.
The processor supports 64 GB (36 bit) of addressable memory space and 64 KB+3 of
addressable I/O space. The CPU performs decoding that historically occurred within the
GMCH. Specifically, the GMCH address decoding for CPU initiated PAM, 15 M-16 M ISA
hole, SMM CSEG/TSEG, PCIexBAR, and DRAM accesses will occur within the CPU and
the GMCH has no direct knowledge. In addition, the Intel® Management Engine
(Intel® ME) will move to the PCH, so Intel ME associated register ranges have been
removed from the Graphics Controller. This section focuses on how the memory space
is partitioned and what the separate memory regions are used for. I/O address space
has simpler mapping and is explained near the end of this section.
The processor supports PEG (PCI Express Graphics) port upper prefetchable base/limit
registers. This allows the PEG unit to claim IO accesses above 32 bit, complying with
the PCI Express Spec. Addressing of greater than 4 GB is allowed on either the DMI
Interface or PCI Express interface. The MCP supports a maximum of 16 GB of DRAM.
No DRAM memory is accessible above 16 GB. DRAM capacity is limited by the number
of address pins available.
RW-O
RW-O-S
W
W1C
Item
Read/Write Once bit(s). Reads prior to the first write return the default
value. The first write after warm reset stores any value written. Any
subsequent write to this bit field is ignored. All subsequent reads return the
first value written. The value returns to default on warm reset. If there are
multiple RW-O or RW-O-S fields within a DWORD, they should be written all at
once (atomically) to avoid capturing an incorrect value.
Read/Write Once/Sticky bit(s). Reads prior to the first write return the
default value. The first write after cold reset stores any value written. Any
subsequent write to this bit field is ignored. All subsequent reads return the
first value written. The value returns to default on cold reset. If there are
multiple RW-O or RW-O-S fields within a DWORD, they should be written all at
once (atomically) to avoid capturing an incorrect value.
Write-only. These bits may be written by software, but will always return
zeros when read. They are used for write side-effects. Any data written to
these registers cannot be retrieved.
Write 1 to Clear-only. These bits may be cleared by software by writing a 1.
Writing a 0 has no effect. The state of the bits cannot be read directly. The
states of such bits are tracked outside the CPU and all read transactions to the
address of such bits are routed to the other agent. Write transactions to these
bits go to both agents.
(Sheet 3 of 3)
Description
Processor Configuration Registers
Datasheet