CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 46

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.7
1.8
46
Warning:
In addition to reserved bits within a register, the processor contains address locations
in the configuration space of the Host Bridge entity that are marked either “Reserved”
or “Intel Reserved”. The processor responds to accesses to Reserved address locations
by completing the host cycle. When a Reserved register location is read, a zero value is
returned. (Reserved registers can be 8, 16, or 32 bits in size). Writes to Reserved
registers have no effect on the processor. Registers that are marked as Intel Reserved
must not be modified by system software. Writes to Intel Reserved registers may cause
system failure. Reads from Intel Reserved registers may return a non-zero value.
Upon a Full Reset, the processor sets its entire set of internal configuration registers to
predetermined default states. Some register values at reset are determined by external
strapping options. The default state represents the minimum functionality feature set
required to successfully bringing up the system. Hence, it does not represent the
optimal system configuration. It is the responsibility of the system initialization
software (usually BIOS) to properly determine the DRAM configurations, operating
parameters and optional system features that are applicable, and to program the
processor registers accordingly.
I/O Mapped Registers
The processor contains two registers that reside in the processor I/O address space 
the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the
configuration space and determines what portion of configuration space is visible
through the Configuration Data window.
PCI Device 0
The DRAM Controller registers are in Device 0 (D0), Function 0 (F0).
Address locations that are not listed are considered Intel Reserved registers locations.
Reads to Reserved registers may return non-zero values. Writes to reserved locations
may cause system failures.
All registers that are defined in the latest PCI Local Bus Specification, but are not
necessary or implemented in this component are simply not included in this document.
The reserved/un-implemented space in the PCI configuration header space is not
documented as such in this summary.
Processor Configuration Registers
Datasheet