CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 97

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.9.17
Datasheet
C0DTC - Channel 0 DRAM Throttling Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Programmable Event weights are input into the averaging filter. Each Event weight is an
normalized 8-bit value that the BIOS must program. The BIOS must account for burst
length and 1N/2N rule considerations. It is also possible for BIOS to take into account
loading variations of memory caused as a function of memory types and population of
ranks.
31:24
18:16
15:8
7:0
Bit
23
22
21
20
19
Access
RW-L-K
RW-L
RW-L
RW-L
RW-L
RW-L
RW-L
RO
RO
Default
Value
000b
00h
00h
00h
0b
0b
0b
0b
0b
Reserved
DRAM Throttle Lock (DTLOCK)
This bit secures the DRAM throttling control
registers DT*EW and DTC. Once a 1 is written to
this bit, all of these configuration register bits
become read-only.
Reserved
Reserved
Reserved
Reserved
Weighted Average Bandwidth Limit (WAB)
Average weighted bandwidth allowed per clock
during for bandwidth based throttling. The
memory controller does not allow any
transactions to proceed on the System Memory
bus if the output of the filter equals or exceeds
this value.
Weighted Average Thermal Limit (WAT)
Average weighted bandwidth allowed per clock
during for thermal sensor enabled throttling. The
memory controller does not allow any
transactions to proceed on the System Memory
bus if the output of the filter equals or exceeds
this value.
0 = Bandwidth Threshold (WAB) is not used for
1 = Bandwidth Threshold (WAB) is used for
If both Bandwidth based and thermal sensor
based throttling modes are on and the thermal
sensor trips, weighted average WAT is used for
throttling.
DRAM Bandwidth Based Throttling Enable
(DBBTE)
throttling.
throttling.
0/0/0/MCHBAR
2B4-2B7h
00000000h
RO; RW-L-K; RW-L
32 bits
Description
97