CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 241

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.16.23
Datasheet
DEVEN - Device Enable
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Allows for enabling/disabling of PCI devices and functions that are within the processor.
The table below the bit definitions describes the behavior of all combinations of
transactions to devices controlled by this register. All the bits in this register are Intel
TXT Lockable.
31:15
7:4
Bit
14
13
12
11
10
9
8
3
2
1
0
Access
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
00000h
Value
0b
0b
0b
0b
0b
0b
1b
0h
1b
0b
1b
1b
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Internal Graphics Engine Function 0 (D2F0EN)
0 = Bus 0 Device 2 Function 0 is disabled and hidden
1 = Bus 0 Device 2 Function 0 is enabled and visible
If this processor does not have internal graphics capability
then Device 2 Function 0 is disabled and hidden independent
of the state of this bit.
Reserved
PCI Express Port (D1EN)
0 = Bus 0 Device 1 Function 0 is disabled and hidden.
1 = Bus 0 Device 1 Function 0 is enabled and visible.
Default value is determined by the device capabilities, SDVO
Presence HW strap and the sDVO/PCIe Concurrent HW strap.
Device 1 is Disabled on Reset if the SDVO Presence strap was
sampled high, and the sDVO/PCIe Concurrent strap was
sampled low at the last assertion of PWROK, and is enabled
by default otherwise.
Host Bridge (D0EN)
Bus 0 Device 0 Function 0 may not be disabled and is
therefore hard wired to 1.
0/2/0/PCI
54-57h
0000210Bh
RO
32 bits
Description
241