CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 147
CP80617004119AES LBU3
Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet
1.CP80617004119AES_LBU3.pdf
(388 pages)
Specifications of CP80617004119AES LBU3
Lead Free Status / RoHS Status
Compliant
- Current page: 147 of 388
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Processor Configuration Registers
1.12.2
1.12.3
Datasheet
SLFRCS - Self-Refresh Channel Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register is Reset by PWROK only.
DSLFRC - PM Memory Subsystem
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
15:11
15:2
9:8
7:3
Bit
Bit
10
1
0
2
1
0
Access
Access
RWC-P
RWC-P
RW
RW
RW
RW
RW
RO
RO
RO
Default
Default
Value
0000h
Value
00h
11b
00h
0b
0b
0b
0b
0b
0b
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0/0/0/MCHBAR
1211-1212h
0000h
RWC-P; RO
16 bits
0/0/0/MCHBAR
120C-120Dh
0300h
16 bits
Reserved
Reserved
0 = Memory is not allowed to enter self-refresh during
1 = Memory is allowed to enter self-refresh during C3/
C-state Dependency for Self Refresh (CXSR)
RO; RW
Description
C3/C6/
C6/
Description
147
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