CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 378

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.20.25
1.20.26
378
IEADDR_REG - Invalidation Completion Event Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the Invalidation Event Interrupt message address. This register is
treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
IEUADDR_REG - Invalidation Completion Event Upper
Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the Invalidation Event interrupt message upper address. This
register is treated as RsvdZ by implementations reporting both Queued Invalidation
(QI) and Extended Interrupt Mode (EIM) as not supported in the Extended Capability
register.
31:0
Bit
Access
RO
00000000h
Default
Value
Message Upper Address (MUA)
Hardware implementations supporting Queued
Invalidations and Extended Interrupt Mode are required to
implement this register.
Hardware implementations not supporting Queued
Invalidations and Extended Interrupt Mode may treat this
field as RsvdZ.
0/2/0/GFXVTBAR
A8-ABh
00000000h
RO
32 bits
0/2/0/GFXVTBAR
AC-AFh
00000000h
RO
32 bits
Processor Configuration Registers
Description
Datasheet