CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 250

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.16.36
1.17
250
MMIO Address
Register
MMIO Data
Register
Register Name
ASLS - ASL Storage
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This software scratch register only needs to be read/write accessible. The exact bit
register usage must be worked out in common between System BIOS and driver
software, but storage for switching/indicating up to six devices is possible with this
amount.
For each device, the ASL control method with require two bits for _DOD (BIOS
detectable yes or no, VGA/NonVGA), one bit for _DGS (enable/disable requested), and
two bits for _DCS (enabled now/disabled now, connected or not).
Device 2 IO
31:0
Bit
Register
Symbol
Access
Index
Data
RW
00000000h Device Switching Storage (DSS)
Default
Value
Register
Start
0
4
Software controlled usage to support device switching.
0/2/0/PCI
FC-FFh
00000000h
RW
32 bits
Register End
3
7
Processor Configuration Registers
Description
Default Value
00000000h
00000000h
Access
RW
RW
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