CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 83

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.9.3
Datasheet
C0DRB0 - Channel 0 DRAM Rank Boundary Address 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The DRAM Rank Boundary Registers define the upper boundary address of each DRAM
rank with a granularity of 64 MB. Each rank has its own single-word DRB register. These
registers are used to determine which chip select is active for a given address. Channel
and rank map:
Programming guide:
15:10
9:0
Bit
Ch0 Rank0:200h
Ch0 Rank1:202h
Ch0 Rank2:204h
Ch0 Rank3:206h
Ch1 Rank0:600h
Ch1 Rank1:602h
Ch1 Rank2:604h
Ch1 Rank3:606h
If Channel 0 is empty, all of the C0DRBs are programmed with 00h.
C0DRB0 = Total memory in Channel 0 Rank 0 (in 64-MB increments)
C0DRB1 = Total memory in Channel 0 Rank 0 + Channel 0 Rank 1 (in 64-MB
increments) and so on.
If Channel 1 is empty, all of the C1DRBs are programmed with 00h.
C1DRB0 = Total memory in Channel 1 Rank 0 (in 64-MB increments)
C1DRB1 = Total memory in Channel 1 Rank 0 + Channel 1 Rank 1 (in 64-MB
increments) and so on.
Access
RW-L
RO
Default
Value
000h
00h
Reserved
Channel 0 DRAM Rank Boundary Address 0
(C0DRBA0)
This register defines the DRAM rank boundary for Rank 0 of
Channel 0 (64-MB granularity) = R0
R0 = Total Rank 0 memory size/64 MB
R1 = Total Rank 1 memory size/64 MB
R2 = Total Rank 2 memory size/64 MB
R3 = Total Rank 3 memory size/64 MB
This register is locked by Intel ME stolen Memory lock.
0/0/0/MCHBAR
200-201h
0000h
RW-L; RO
16 bits
Description
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