CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 153

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
Bit
6
5
4
3
2
1
0
Access
RW
RW
RW
RW
RO
RO
RO
Default
Value
0b
0b
0b
0b
0b
0b
0b
Parity Error Response Enable (PERRE)
Controls whether or not the Master Data Parity Error bit in
the PCI Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register
1 = Master Data Parity Error bit in PCI Status register CAN
VGA Palette Snoop (VGAPS)
Not Applicable or Implemented. Hard wired to 0.
Memory Write and Invalidate Enable (MWIE)
Not Applicable or Implemented. Hard wired to 0.
Special Cycle Enable (SCE)
Not Applicable or Implemented. hard wired to 0.
Bus Master Enable (BME)
Controls the ability of the PEG port to forward Memory and
IO Read/Write Requests in the upstream direction.
0 = This device is prevented from making memory or IO
1 = This device is allowed to issue requests to its primary
Memory Access Enable (MAE)
0 = All of Device 1's memory space is disabled.
1 = Enable the Memory and Pre-fetchable memory address
IO Access Enable (IOAE)
0 = All of Device 1's I/O space is disabled.
1 = Enable the I/O address range defined in the IOBASE1,
CANNOT be set.
be set.
requests to its primary bus. Note that according to the
PCI Local Bus Specification, as MSI interrupt messages
are in-band memory writes, disabling the bus master
enable bit prevents this device from generating MSI
interrupt messages or passing them from its secondary
bus to its primary bus. Upstream memory writes/reads,
IO writes/reads, peer writes/reads, and MSIs will all be
treated as illegal cycles. Writes are forwarded to
memory address C0000h with byte enables deasserted.
Reads is forwarded to memory address C0000h and will
return Unsupported Request status (or Master abort) in
its completion packet.
bus. Completions for previously issued memory read
requests on the primary bus is issued when the data is
available. This bit does not affect forwarding of
Completions from the primary interface to the
secondary interface.
ranges defined in the MBASE1, MLIMIT1, PMBASE1, and
PMLIMIT1 registers.
and IOLIMIT1 registers.
(Sheet 2 of 2)
Description
153