CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 7

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Datasheet
1.16
1.17
1.18
1.15.12DMILCTL - DMI Link Control ................................................................... 221
1.15.13DMILSTS - DMI Link Status.................................................................... 222
PCI Device 2 Function 0 ................................................................................... 222
1.16.1 VID2 - Vendor Identification .................................................................. 224
1.16.2 DID2 - Device Identification ................................................................... 225
1.16.3 PCICMD2 - PCI Command...................................................................... 225
1.16.4 PCISTS2 - PCI Status............................................................................ 226
1.16.5 RID2 - Revision Identification................................................................. 228
1.16.6 CC - Class Code ................................................................................... 229
1.16.7 CLS - Cache Line Size ........................................................................... 230
1.16.8 MLT2 - Master Latency Timer ................................................................. 230
1.16.9 HDR2 - Header Type ............................................................................. 231
1.16.10GTTMMADR - Graphics Translation Table, Memory Mapped Range Address ... 231
1.16.11GMADR - Graphics Memory Range Address .............................................. 232
1.16.12IOBAR - I/O Base Address ..................................................................... 233
1.16.13SVID2 - Subsystem Vendor Identification ................................................ 234
1.16.14SID2 - Subsystem Identification ............................................................. 234
1.16.15ROMADR - Video BIOS ROM Base Address ............................................... 235
1.16.16CAPPOINT - Capabilities Pointer.............................................................. 235
1.16.17INTRLINE - Interrupt Line ...................................................................... 236
1.16.18INTRPIN - Interrupt Pin ......................................................................... 236
1.16.19MINGNT - Minimum Grant ..................................................................... 236
1.16.20MAXLAT - Maximum Latency .................................................................. 237
1.16.21GGCTL - Graphics Enhanced Intel® SpeedStep Technology Capability ......... 237
1.16.22MGGC - Processor Graphics Control Register ............................................ 239
1.16.23DEVEN - Device Enable ......................................................................... 241
1.16.24SSRW - Software Scratch Read Write ...................................................... 242
1.16.25BSM - Base of Stolen Memory ................................................................ 242
1.16.26HSRW - Hardware Scratch Read Write ..................................................... 242
1.16.27MSAC - Multi Size Aperture Control ......................................................... 243
1.16.28MC - Message Control ........................................................................... 243
1.16.29MA - Message Address .......................................................................... 245
1.16.30MD - Message Data............................................................................... 245
1.16.31PMCAPID - Power Management Capabilities ID ......................................... 246
1.16.32PMCAP - Power Management Capabilities ................................................. 246
1.16.33PMCS - Power Management Control/Status .............................................. 247
1.16.34SWSMI - Software SMI.......................................................................... 248
1.16.35GSE - Graphics System Event Register .................................................... 249
1.16.36ASLS - ASL Storage .............................................................................. 250
Device 2 IO .................................................................................................... 250
1.17.1 Index - MMIO Address Register .............................................................. 251
1.17.2 Data - MMIO Data Register .................................................................... 251
DMI and PEG VC0/VCp Remap Registers............................................................. 252
1.18.1 VER_REG - Version Register................................................................... 254
1.18.2 CAP_REG - Capability Register ............................................................... 255
1.18.3 ECAP_REG - Extended Capability Register ................................................ 258
1.18.4 GCMD_REG - Global Command Register .................................................. 261
1.18.5 GSTS_REG - Global Status Register ........................................................ 265
1.18.6 RTADDR_REG - Root-Entry Table Address Register.................................... 267
1.18.7 CCMD_REG - Context Command Register ................................................ 268
1.18.8 FSTS_REG - Fault Status Register........................................................... 271
1.18.9 FECTL_REG - Fault Event Control Register ............................................... 273
1.18.10FEDATA_REG - Fault Event Data Register ................................................ 275
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