CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 68

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.8.21
68
TOUUD - Top of Upper Usable DRAM
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This 16-bit register defines the Top of Upper Usable DRAM.
Configuration software must set this value to TOM minus all EP stolen memory aligned
down to a 64-MB boundary. If reclaim is enabled, this value must be set to reclaim limit
64-MB aligned, since reclaim limit + 1 byte is 64-MB aligned. Address Bits 19:0 are
assumed to be 000_0000h for the purposes of address comparison. The Host interface
positively decodes an address towards DRAM if the incoming address is less than the
value programmed in this register and greater than 4 GB.
These bits are Intel TXT lockable.
15:0
Bit
Access
RW-L
Default
0000h
Value
TOUUD (TOUUD)
This register contains Bits 35:20 of an address one byte above
the maximum DRAM memory above 4 GB that is usable by the
operating system. Configuration software must set this value
to TOM minus all EP stolen memory if reclaim is disabled. If
reclaim is enabled, this value must be set to reclaim limit 64-
MB aligned since reclaim limit + 1 byte is 64-MB aligned.
Address Bits 19:0 are assumed to be 000_0000h for the
purposes of address comparison. The Host interface positively
decodes an address towards DRAM if the incoming address is
less than the value programmed in this register and greater
than 4 GB.
All the bits in this register are locked in Intel VT-d mode.
0/0/0/PCI
A2-A3h
0000h
RW-L
16 bits
Description
Processor Configuration Registers
Datasheet