CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 245

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.16.29
1.16.30
Datasheet
MA - Message Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
MD - Message Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:2
15:0
1:0
Bit
Bit
Access
Access
RW
RO
RW
00000000h
Default
Value
Default
Value
0000h
00b
FLR, Core
FLR, Core
RST/
PWR
Core
RST/
PWR
0/2/0/PCI
94-97h
00000000h
RO; RW
32 bits
0/2/0/PCI
98-99h
0000h
RW
16 bits
Message Address (MESSADD)
Used by system software to assign an MSI
address to the device.
The device handles an MSI by writing the padded
contents of the MD register to this address.
Force Dword Align (FDWORD)
system software are always aligned on a DWORD
address boundary.
hard wired to 0 so that addresses assigned by
Message Data (MESSDATA)
Base message data pattern assigned by system
software and used to handle an MSI from the
device.
When the device must generate an interrupt
request, it writes a 32-bit value to the memory
address specified in the MA register. The upper
16 bits are always set to 0. The lower 16 bits
are supplied by this register.
Description
Description
245