CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 130

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.10.14
130
TINTRCMD - Thermal INTR Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register selects specific errors to generate an INT DMI cycle
7:6
Bit
5
4
3
2
1
0
Access
RW
RW
RW
RW
RW
RW
RO
Default
Value
00b
0b
0b
0b
0b
0b
0b
Reserved
INTR on Catastrophic Thermal Sensor Trip (CATINTR)
1 = INTR DMI cycle is generated by the memory controller
INTR on Hot Thermal Sensor Trip (HOTINTR)
1 = INTR DMI cycle is generated by the memory controller
INTR on AUX3 Thermal Sensor Trip (AUX3INTR)
1 = INTR DMI cycle is generated by the memory controller
INTR on AUX2 Thermal Sensor Trip (AUX2INTR)
1 = INTR DMI cycle is generated by the memory controller
INTR on AUX1 Thermal Sensor Trip (AUX1INTR)
1 = INTR DMI cycle is generated by the memory controller
INTR on AUX0 Thermal Sensor Trip (AUX0INTR)
1 = INTR DMI cycle is generated by the memory controller
0/0/0/MCHBAR
10E7h
00h
RO; RW
8 bits
Description
Processor Configuration Registers
Datasheet