CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 193

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.13.43
Datasheet
SLOTSTS - Slot Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
PCI Express Slot related registers allow for the support of Hot Plug.
15:9
Bit
Bit
3
2
1
0
8
Access
Access
RW
RO
RO
RO
RO
RO
0000000b
Default
Default
Value
Value
0b
0b
0b
0b
0b
Presence Detect Changed Enable (PDCE)
When set to 1b, this bit enables software notification on a
presence detect changed event.
Reserved for MRL Sensor Changed Enable (MSCE)
When set to 1b, this bit enables software notification on a
MRL sensor changed event.
Default value of this field is 0b. If the MRL Sensor Present
field in the Slot Capabilities register is set to 0b, this bit is
permitted to be read-only with a value of 0b.
Reserved for Power Fault Detected Enable (PFDE)
When set to 1b, this bit enables software notification on a
power fault event.
Default value of this field is 0b. If Power Fault detection is not
supported, this bit is permitted to be read-only with a value of
0b
Reserved for Attention Button Pressed Enable (ABPE)
When set to 1b, this bit enables software notification on an
attention button pressed event.
Reserved and Zero
For future R/WC/S implementations; software must use 0 for
writes to bits.
Reserved for Data Link Layer State Changed (DLLSC)
This bit is set when the value reported in the Data Link Layer
Link Active field of the Link Status register is changed. In
response to a Data Link Layer State Changed event, software
must read the Data Link Layer Link Active field of the Link
Status register to determine if the link is active before
initiating configuration cycles to the hot plugged device.
0/1/0/PCI
BA-BBh
0000h
RO; RWC
16 bits
(Sheet 3 of 3)
(Sheet 1 of 3)
Description
Description
193