CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 42

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.5
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To access this space (step 1 is done only once by BIOS):
Routing Configuration Accesses
The processor supports two PCI related interfaces: DMI and PCI Express. The processor
is responsible for routing PCI and PCI Express configuration cycles to the appropriate
device that is an integrated part of the processor or to one of these two interfaces.
Configuration cycles to the PCH internal devices and Primary PCI (including
downstream devices) are routed to the PCH via DMI. Configuration cycles to both the
PCI Express Graphics PCI compatibility configuration space and the PCI Express
Graphics extended configuration space are routed to the PCI Express Graphics port
device or associated link.
1. Write to CSR address 0x01050 to enable the PCI Express enhanced configuration
2. Calculate the host address of the register you wish to set using (PCI Express base
3. Use a memory write or memory read cycle to the calculated host address to write
mechanism by writing 1 to Bit 0 of the GQ1_CR_PCIEXBAR register. Allocate either
256, 128, or 64 busses to PCI Express by writing “000”, “111”, or “110”
respectively to Bits 3:1. Pick a naturally aligned base address for mapping the
configuration space onto memory space using 1 MB per bus number and write that
base address into Bits 39:20.
+ (bus number * 1 MB) + (device number * 32 KB) + (function number * 4 KB) +
(1 B * offset within the function) = host address)
or read that register.
Processor Configuration Registers
Datasheet