CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 75

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.8.29
Datasheet
ERRCMD - Error Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the memory controller responses to various system errors. Since
the processor does not have an SERRB signal, SERR messages are passed from the
Processor to the PCH over DMI.
When a bit in this register is set, a SERR message is generated on DMI whenever the
corresponding flag is set in the ERRSTS register. The actual generation of the SERR
message is globally enabled for Device 0 via the PCI Command register.
15:12
6:2
Bit
11
10
9
8
7
1
0
Access
RW
RW
RW
RW
RW
RW
RO
RO
RO
Default
Value
00h
0h
0b
0b
0b
0b
0b
0b
0b
Reserved
SERR on Memory Controller Thermal Sensor Event
(TSESERR)
0 = Reporting of this condition via SERR messaging is
1 = The Memory controller generates a DMI SERR special
Reserved
SERR on LOCK to non-DRAM Memory (LCKERR)
0 = Reporting of this condition via SERR messaging is
1 = The memory controller will generate a DMI SERR special
Reserved
SERR on DRAM Throttle Condition (
ERR)
0 = Reporting of this condition via SERR messaging is
1 = The memory controller generates a DMI SERR special
Reserved
Reserved
Reserved
0/0/0/PCI
CA-CBh
0000h
RO; RW
16 bits
disabled.
cycle when Bit 11 of the ERRSTS is set. The SERR must
not be enabled at the same time as the SMI for the
same thermal sensor event.
disabled
cycle whenever a CPU lock cycle is detected that does
not hit DRAM.
disabled.
cycle when a DRAM Read or Write Throttle condition
occurs.
Description
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