CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 126

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

126
3:0
Bit
Access
RW
Default
Value
0h
Thermometer Mode Enable and Rate (TE)
If analog thermal sensor mode is not enabled by setting
these bits to 0000b, these bits enable the thermometer mode
functions and set the Thermometer controller rate. When the
Thermometer mode is disabled and TSC1[TSC] =enabled, the
analog sensor mode should be fully functional.
In the analog sensor mode, the Catastrophic trip is
functional. The other trip points are not functional in this
mode.
When Thermometer mode is enabled, all the trip points
(Catastrophic, Hot, Aux0, Aux1, Aux2 will all operate using
the programmed trip points and Thermometer mode rate.
NOTES:
1.
2.
Thermometer rate select (i.e., AST clock select)
0000 = Thermometer mode disabled (i.e., analog sensor
mode)
0001 = Enabled, 2 µsec (normal thermometer mode
operation, pre-silicon)
0010 = Enabled, 4 µsec
0011 = Enabled, 6 µsec
0100 = Enabled, 8 µsec
0101 = Enabled, 10 µsec
0110 = Enabled, 12 µsec
0111 = Enabled, 14 µsec
All others reserved.
When disabling the Thermometer mode while
thermometer running, the Thermometer mode controller
will finish the current cycle.
During boot, all other thermometer mode registers
(except lock bits) should be programmed appropriately
before enabling the Thermometer Mode.
Description
Processor Configuration Registers
Datasheet