CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 307

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
17:8
Bit
7
6
5
4
3
2
1
Access
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
010h
0b
0b
0b
0b
0b
0b
0b
Invalidation Unit Offset (IVO)
This field specifies the location to the first IOTLB registers
relative to the register base address of this DMA-remapping
hardware unit.
If the register base address is X, and the value reported in
this field is Y, the address for the first IOTLB register is
calculated as X+(16*Y).
Snoop Control (SC)
0 = Hardware does not support setting the SNP field to 1 in
1 = Hardware supports setting the SNP field to 1 in the
Pass Through (PT)
0 = Hardware does not support pass-through translation
1 = Hardware supports pass-through translation type in
Caching Hints (CH)
0 = Hardware does not support IOTLB caching hints (ALH
1 = Hardware supports IOLTB caching hints through the ALH
Extended Interrupt Mode (EIM)
0 = On Intel®64 platforms, hardware supports only 8-bit
1 = On Intel®64 platforms, hardware supports 32-bit APIC-
Itanium® processor platforms support 16-bit APICIDs and
always report this field as 0.
This field is valid only when the IR field is reported as Set.
Device IOTLB Support (DI)
1 = Hardware does not support device-IOTLBs.
0 = Hardware supports Device-IOTLBs.
Implementations reporting this field as Set must also
support Queued Invalidation (QI = 1b).
Queued Invalidation Support (QI)
0 = Hardware does not support queued invalidations.
1 = Hardware supports queued invalidations.
0 = Hardware does not support interrupt remapping.
1 = Hardware supports interrupt remapping.
Implementations reporting this field as Set must also
support Queued Invalidation (QI = 1b).
Interrupt Remapping Support (IR)
the page-table entries.
page-table entries.
type in context entries.
context entries.
and EH fields in context-entries are treated as
reserved).
and EH fields in context-entries.
APIC-IDs (xAPIC Mode).
IDs (x2APIC mode).
(Sheet 2 of 3)
Description
307