CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 288

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.18.28
288
IVA_REG - Invalidate Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to provide the DMA address whose corresponding IOTLB entry needs to be
invalidated through the corresponding IOTLB Invalidate register. This register is a
write-only register. Value returned on reads of this register is undefined. There is an
IVA_REG for each IOTLB Invalidation unit supported by hardware.
63:12
10:4
11:7
3:0
Bit
Bit
11
Access
Access
RW
RW
RO
RO
W
00000000
Default
Default
00000h
Value
Value
00h
00h
0b
0h
Reserved
Size (S)
This field specifies the size of the interrupt remapping table.
The number of entries in the interrupt remapping table is
2
Address (Addr)
Software provides the DMA address that needs to be page-
selectively invalidated. To request a page-selective
invalidation request to hardware, software must first write
the appropriate fields in this register, and then issue
appropriate page-selective invalidate command through the
IOTLB_REG.
Hardware ignores Bits 63:N, where N is the maximum guest
address width (MGAW) supported. Value returned on read of
this field is undefined.
Reserved
0 = Legacy interrupt mode is active. Hardware interprets
The high 24 bits of the Destination-ID field is treated as
reserved. On Itanium® processor platforms hardware
interprets low 16- bits of Destination-ID field in the IRTEs
and treats the high 16-bits as reserved.
1 = Intel®64 platform is operating in Extended Interrupt
Hardware reporting Extended Interrupt Mode (EIM) as Clear
in the Capability register treats this field as RsvdZ.
Extended Interrupt Mode Enable (EIMI)
(X+1)
0/0/0/VC0PREMAP
100-107h
0000000000000000h
RO; W
64 bits
only low 8-bits of Destination-ID field in the IRTEs.
Mode. Hardware interprets all 32-bits of the
Destination- ID field in the IRTEs.
(Sheet 1 of 2)
(Sheet 2 of 2)
, where X is the value programmed in this field.
Processor Configuration Registers
Description
Description
Datasheet