CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 230

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.16.7
1.16.8
230
CLS - Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The IGD does not support this register as a PCI slave.
MLT2 - Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
7:0
7:0
Bit
Bit
Access
Access
RO
RO
Default
Default
Value
Value
00h
00h
Master Latency Timer Count Value (MLTCV)
Hard wired to 0’s.
Cache Line Size (CLS)
This field is hard wired to 0’s. The IGD as a PCI compliant
master does not use the Memory Write and Invalidate
command and, in general, does not perform operations
based on cache line size.
0/2/0/PCI
Ch
00h
RO
8 bits
0/2/0/PCI
Dh
00h
RO
8 bits
Processor Configuration Registers
Description
Description
Datasheet