CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 233

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.16.12
Datasheet
IOBAR - I/O Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register provides the Base offset of the I/O registers within Device 2. Bits 15:3 are
programmable allowing the I/O Base to be located anywhere in 16-bit I/O Address
Space. Bits 2:1 are fixed and return zero, Bit 0 is hard wired to a one indicating that 8
bytes of I/O space are decoded. Access to the 8 bytes of IO space is allowed in PM state
D0 when IO Enable (PCICMD bit 0) set. Access is disallowed in PM states D1-D3 or if IO
Enable is clear or if Device 2 is turned off or if internal graphics is disabled thru the fuse
or fuse override mechanisms.
If accesses to this IO bar is allowed then the processor claims all 8-, 16- or 32-bit I/O
cycles from the CPU that falls within the 8B claimed.
26:4
2:1
Bit
28
27
3
0
Access
RW-L
RW-L
RO
RO
RO
RO
000000h
Default
Value
10b
0b
0b
1b
0b
FLR, Core
FLR, Core
RST/
PWR
Core
Core
Core
Core
0/2/0/PCI
20-23h
00000001h
RO; RW
32 bits
(Sheet 2 of 2)
512-MB Address Mask (512ADMSK)
This bit is either part of the Memory Base
Address (R/W) or part of the Address Mask (RO),
depending on the value of MSAC[2:1].
See MSAC (Device 2, Function 0, Offset 62h) for
details.
256-MB Address Mask (256ADMSK)
This bit is either part of the Memory Base
Address (R/W) or part of the Address Mask (RO),
depending on the value of MSAC[2:1]. See MSAC
(Device 2, Function 0, Offset 62h) for details.
Address Mask (ADM)
address range.
Prefetchable Memory (PREFMEM)
Memory Type (MEMTYP)
00: indicate 32-bit address.
10: Indicate 64-bit address
Memory/IO Space (MIOS)
hard wired to 0’s to indicate at least 128-MB
hard wired to 1 to enable prefetching.
hard wired to 0 to indicate memory space.
Description
233