CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 105

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.9.29
Datasheet
C1CYCTRKRD - Channel 1 CYCTRK READ
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 1 CYCTRK READ
23:21
20:17
16:12
11:8
7:4
3:0
Bit
Access
RW
RW
RW
RW
RW
RO
Default
00000b
Value
0000b
0000b
0000b
0h
0h
Reserved
Min ACT-to-READ Delayed (C1sd_cr_act_rd)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the ACT and READ
commands to the same rank-bank
Corresponds to tRCD_rd at DDR Spec.
Same Rank Write-to-READ Delayed
(C1sd_cr_wrsr_rd)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the WRITE and READ
commands to the same rank.
Corresponds to tWTR at DDR Spec.
Different Ranks Write-to-READ Delayed
(C1sd_cr_wrdr_rd)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the WRITE and READ
commands to different ranks.
Corresponds to tWR_RD at DDR Spec.
Same Rank Read-to-Read Delayed (C1sd_cr_rdsr_rd)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two READ commands to
the same rank.
Different Ranks Read-to-Read Delayed
(C1sd_cr_rddr_rd)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two READ commands to
different ranks.
Corresponds to tRD_RD.
0/0/0/MCHBAR
658-65Ah
000000h
RO; RW
24 bits
Description
105