CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 22

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.2.2.4
1.2.2.5
1.2.2.6
1.2.2.6.1
1.2.2.6.2
22
DRAM Protected Range (DPR)
This protection range only applies to DMA accesses and GMADR translations. It serves a
purpose of providing a memory range that is only accessible to CPU streams.
The DPR range works independent of any other range, including the PMRC checks in
Intel VT-d). It occurs post any Intel VT-d translation. Therefore incoming cycles are
checked against this range after the Intel VT-d translation and faulted if they hit this
protected range, even if they passed the Intel VT-d translation.
The system will set up:
After some time, software could request more space for not allowing DMA. It will get
some more pages and make sure there are no DMA cycles to the new region. DPR size
is changed to the new value. When it does this, there should not be any DMA cycles
going to DRAM to the new region.
If there were cycles from a rogue device to the new region, then those could use the
previous decode until the new decode can guarantee PV. No flushing of cycles is
required. On a clock by clock basis proper decode with the previous or new decode
needs to be guaranteed.
All upstream cycles from 0 to (TSEG_BASE – 1 – DPR size), and not in the legacy holes
(VGA), are decoded to DRAM.
Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and
reside within system memory address range (< TOLUD) are created for SMM-mode,
legacy VGA graphics compatibility, and GFX GTT stolen memory. It is the responsibility
of BIOS to properly initialize these regions.
GFX Stolen Spaces
GTT Stolen Space (GSM)
GSM is allocated to store the GFX translation table entries, depending on Intel VT-d
support it may be divided into two sections.
Global GTT Stolen Space (GGSM)
GGSM always exists regardless of Intel VT-d as long as internal GFX is enabled. This
space is allocated to store accesses as page table entries are getting updated through
virtual GTTMMADR range. Hardware is responsible to map PTEs into this physical space.
1. 0 to (TSEG_BASE – DPR size – 1) for DMA traffic
2. TSEG_BASE
3. to (TSEG_BASE – DPR size) as no DMA.
Processor Configuration Registers
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