CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 271

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.18.8
Datasheet
FSTS_REG - Fault Status Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register indicating the primary fault logging status.
31:16
15:8
Bit
7
6
5
4
Access
RWC-P
RWC-P
RWC-P
RO-P
RO
RO
Default
Value
0000h
00h
0b
0b
0b
0b
Reserved
Fault Record Index (FRI)
This field is valid only when the PPF field is set.
The FRI field indicates the index (from base) of the fault
recording register to which the first pending fault was
recorded when the PPF field was set by hardware. Valid
values for this field are from 0 to N, where N is the value
reported through NFR field in the Capability register.
The value read from this field is undefined when the PPF field
is clear.
Reserved
Invalidation Time-out Error (ITE)
Hardware detected a Device-IOTLB invalidation completion
time-out. At this time, a fault event may be generated based
on the programming of the Fault Event Control register.
Hardware implementations not supporting Device- IOTLBs
implement this bit as RSVD.
Invalidation Completion Error (ICE)
Hardware received an unexpected or invalid Device-IOTLB
invalidation completion. This could be due to either an
invalid ITag or invalid source-id in an invalidation completion
response. At this time, a fault event may be generated
based on the programming of the Fault Event Control
register.
Hardware implementations not supporting Device-IOTLBs
implement this bit as RSVD
Invalidation Queue Error (IQE)
Hardware detected an error associated with the invalidation
queue. This could be due to either a hardware error while
fetching a descriptor from the invalidation queue, or
hardware detecting an erroneous or invalid descriptor in the
invalidation queue. At this time, a fault event may be
generated based on the programming of the Fault Event
Control register.
Hardware implementations not supporting queued
invalidations implement this bit as RSVD.
0/0/0/VC0PREMAP
34-37h
00000000h
RO; RO-P; RWC-P
32 bits
(Sheet 1 of 2)
Description
271