CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 33
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CP80617004119AES LBU3
Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet
1.CP80617004119AES_LBU3.pdf
(388 pages)
Specifications of CP80617004119AES LBU3
Lead Free Status / RoHS Status
Compliant
- Current page: 33 of 388
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Processor Configuration Registers
1.2.3.1.4
Datasheet
Figure 8.
Case #4: Greater Than 4 GB of Physical Memory, Remap
More Than 4 GB, Remap Enabled
In this case the amount of memory remapped is the range between TOLUD and 4 GB.
This physical memory is mapped to the logical address range defined between the
REMAPBASE and the REMAPLIMIT registers.
Example: 5 GB of Physical Memory, with 1 GB allocated to Memory Mapped IO:
•
•
•
•
•
•
Populated Physical Memory = 5 GB
Address Space allocated to memory mapped IO = 1 GB
Remapped Physical Memory = 1 GB
TOM – 050h (5 GB)
Intel ME stolen size – 00000b (0 MB)
TOUUD – 17FFh (6GB-1 MB) (1 MB aligned)
RECLAIM BASE + x
RECLAIM LIMIT =
RECLAIM BASE
64 MB aligned
64 MB aligned
TOLUD BASE
HOST/SYSTEM VIEW
64 MB aligned
64 GB
0
PCI MMIO
MEMORY
RECLAIM
REGION
HMMIO
ABOVE
DRAM”
DRAM
TSEG
“LOW
4 GB
X
4 GB
GFX GTT Stolen BASE
GFX Stolen BASE
EP Stolen BASE
(DRAM CONTROLLER VIEW)
TSEG BASE
TOM
PHYSICAL MEMORY
0
INVISIBLE
(1-64 MB)
RECLAIM
(0-64 MB)
GFX GTT
(0-64 MB)
EP-UMA
STOLEN
(0-8 MB)
VISIBLE
VISIBLE
Wasted
0 MB –
< 4 GB
63 MB
>4 GB
TSEG
GFX
OS
OS
OS
64 MB aligned
64 MB aligned
1 MB aligned
1 MB aligned
64 MB aligned for reclaim
1 MB aligned
1 MB aligned
33
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