CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 34

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.2.4
1.2.5
34
PCI Express* Configuration Address Space
PCIEXBAR has moved to the CPU. The CPU now detects memory accesses targeting
PCIEXBAR. BIOS must assign this address range such that it will not conflict with any
other address ranges.
PCI Express Graphics Attach (PEG)
The GMCH can be programmed to direct memory accesses to a PCI Express interface.
When addresses are within either of two ranges specified via registers in each PEG(s)
configuration space.
Conceptually, address decoding for each range follows the same basic concept. The top
12 bits of the respective Memory Base and Memory Limit registers correspond to
address bits A[31:20] of a memory address. For the purpose of address decoding, the
GMCH assumes that address bits A[19:0] of the memory base are zero and that
address bits A[19:0] of the memory limit address are F_FFFFh. This forces each
memory address range to be aligned to 1-MB boundary and to have a size granularity
of 1 MB.
The GMCH positively decodes memory accesses to PCI Express memory address space
as defined by the following equations:
Memory_Base_Address  Address  Memory_Limit_Address
Prefetchable_Memory_Base_Address  Address  Prefetchable_Memory_Limit_Address
The window size is programmed by the plug-and-play configuration software. The
window size depends on the size of memory claimed by the PCI Express device.
Normally these ranges will reside above the Top-of-Low Usable-DRAM and below High
BIOS and APIC address ranges. They must reside above the top of low memory
(TOLUD) if they reside below 4 GB and must reside above top of upper memory
(TOUUD) if they reside above 4 GB or they will steal physical DRAM memory space.
It is essential to support a separate Pre-fetchable range in order to apply USWC
attribute (from the processor point of view) to that range. The USWC attribute is used
by the processor for write combining.
•
•
•
•
•
TOLUD – 06000h (3 GB) (64 MB aligned because remap is enabled and the remap
register has 64MB granularity)
REMAPBASE – 050h (5 GB)
REMAPLIMIT – 05Fh (6 GB – 1 boundary)
The first range is controlled via the Memory Base Register (MBASE) and Memory
Limit Register (MLIMIT) registers.
The second range is controlled via the Pre-fetchable Memory Base (PMBASE) and
Pre-fetchable Memory Limit (PMLIMIT) registers.
Processor Configuration Registers
Datasheet