CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 140

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.10.23
140
MTDPCHOTTHINT2 - Memory TDP Controller Hot Throttled
Intervals 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:24
23:16
15:8
7:0
Bit
Access
RW
RW
RW
RW
Default
Value
00h
00h
00h
00h
Memory IFC Hot Minus 4 Throttle Interval
(MIHOTM4ThrotInt)
The number of clocks, memory would be throttled for Rd
or Wr operations within the period defined by the
MITNTInt register field, when the Hot-4 threshold is
tripped.
Memory IFC Hot Minus 5 Throttle Interval
(MIHOTM5ThrotInt)
The number of clocks, memory would be throttled for Rd
or Wr operations within the period defined by the
MITNTInt register field, when the Hot-5 threshold is
tripped.
Memory IFC Hot Minus 6 Throttle Interval
(MIHOTM6ThrotIn)
The number of clocks, memory would be throttled for Rd
or Wr operations within the period defined by the
MITNTInt register field, when the Hot-6 threshold is
tripped.
Memory IFC Hot Minus 7 Throttle Interval
(MIHOTM7ThrotInt)
The number of clocks, memory would be throttled for Rd
or Wr operations within the period defined by the
MITNTInt register field, when the Hot-7 threshold is
tripped.
0/0/0/MCHBAR
304-307h
00000000h
32 bits
RW
Processor Configuration Registers
Description
Datasheet