CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 152

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.13.3
152
PCICMD1 - PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
15:11
Bit
10
9
8
7
Access
RW
RW
RO
RO
RO
Default
Value
00h
0b
0b
0b
0b
Reserved
INTA Assertion Disable (INTAAD)
0 = This device is permitted to generate INTA interrupt
1 = This device is prevented from generating interrupt
Only affects interrupts generated by the device (PCI INTA
from a PME or Hot Plug event) controlled by this command
register. It does not affect upstream MSIs, upstream PCI
INTA-INTD assert and deassert messages.
Fast Back-to-Back Enable (FB2B)
Not Applicable or Implemented. hard wired to 0.
SERR# Message Enable (SERRE1)
Controls Device 1 SERR# messaging. The processor
communicates the SERR# condition by sending an SERR
message to the PCH. This bit, when set, enables reporting
of non-fatal and fatal errors detected by the device to the
Root Complex. Note that errors are reported if enabled
either through this bit or through the PCI-Express specific
bits in the Device Control Register.
In addition, for Type 1 configuration space header devices,
this bit, when set, enables transmission by the primary
interface of ERR_NONFATAL and ERR_FATAL error messages
forwarded from the secondary interface. This bit does not
affect the transmission of forwarded ERR_COR messages.
0 = The SERR message is generated by the processor for
1 = The processor is enabled to generate SERR messages
Reserved
Not Applicable or Implemented. Hard wired to 0.
0/1/0/PCI
4-5h
0000h
RO; RW
16 bits
messages.
messages. Any INTA emulation interrupts already
asserted must be de-asserted when this bit is set.
Device 1 only under conditions enabled individually
through the Device Control Register.
which is sent to the PCH for specific Device 1 error
conditions generated/detected on the primary side of
the virtual PCI to PCI bridge (not those received by the
secondary side). The status of SERRs generated is
reported in the PCISTS1 register.
(Sheet 1 of 2)
Processor Configuration Registers
Description
Datasheet