CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 210

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CP80617004119AES LBU3

Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet

Specifications of CP80617004119AES LBU3

Lead Free Status / RoHS Status
Compliant
210
25:21
20:17
16:13
12:8
Bit
Access
RW
RW
RO
RO
Default
11111b
01011b
0000b
0000b
Value
Transmit Driver Enable For Gen2
(TXDGEN2DRVEN) Default of TXDGEN2SEL and
TXDGEN2DRVEN provides -3.5dB of de-emphasis.
Reserved
Reserved
Transmit De-emphasis For Gen1 (TXDGEN1SEL)
Default of TXDGEN1SEL and TXDGEN1DRVEN provides
-3.5dB of de-emphasis.The following are the production
settings:
(Sheet 3 of 4)
Input Code
00000b
00001b
00010b
00011b
00100b
00101b
00110b
00111b
01000b
01001b
01010b
01011b
01100b
01101b
01110b
01111b
10000b
10001b
10010b
10011b
10100b
10101b
10110b
10111b
11000b
11001b
11010b
11011b
11100b
11101b
11110b
11111b
De-emphasis
0dB
-0.37dB
-0.76dB
-1.16dB
-1.58dB
-2.03dB
-2.50dB
-3.00dB
-2.03dB
-2.50dB
-3.00dB
-3.52dB
-4.08dB
-4.68dB
-5.33dB
-6.02dB
-6.02dB
-6.78dB
-7.60dB
-8.52dB
-9.54dB
-10.70dB
-12.04dB
-13.62dB
-10.70dB
-12.04dB
-13.62dB
-15.56dB
-18.06dB
-21.58dB
-27.60dB
N/A
Processor Configuration Registers
Description
Gen1 Default
Notes
Gen2 Default
No de-emphasis
Not Valid
Datasheet

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