CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 220

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.15.11
220
DMILCAP - DMI Link Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Indicates DMI specific capabilities.
31:18
17:15
14:12
11:10
9:4
3:0
Bit
Access
RW-O
RW-O
RO
RO
RO
RO
Default
Value
0000h
010b
010b
11b
04h
1h
Reserved
L1 Exit Latency (L1SELAT)
Indicates the length of time this Port requires to complete the
transition from L1 to L0. The value 010b indicates the range
of 2 µs to less than 4 µs.
Both bytes of this register that contain a portion of this field
must be written simultaneously in order to prevent an
intermediate (and undesired) value from ever existing.
L0s Exit Latency (L0SELAT)
Indicates the length of time this Port requires to complete the
transition from L0s to L0.
Active State Link PM Support (ASLPMS)
L0s & L1 entry supported.
Max Link Width (MLW)
Indicates the maximum number of lanes supported for this
link.
Max Link Speed (MLS)
hard wired to indicate 2.5 Gb/s.
000:Less than 1 µs
001:1 µs to less than 2 µs
010:2 µs to less than 4 µs
011:4 µs to less than 8 µs
100:8 µs to less than 16 µs
101:16 µs to less than 32 µs
110:32 µs-64 µs
111:More than 64 µs
000:Less than 64 ns
001:64 ns to less than 128 ns
010:128 ns to less than 256 ns
011:256 ns to less than 512 ns
100:512 ns to less than 1 µs
101:1 µs to less than 2 µs
110:2 µs-4 µs
111:More than 4 µs
0/0/0/DMIBAR
84-87h
00012C41h
RO; RW-O
32 bits
Description
Processor Configuration Registers
Datasheet