CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 155

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CP80617004119AES LBU3

Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet

Specifications of CP80617004119AES LBU3

Lead Free Status / RoHS Status
Compliant
Processor Configuration Registers
Datasheet
2:0
Bit
7
6
5
4
3
Access
RO
RO
RO
RO
RO
RO
Default
Value
000b
0b
0b
0b
1b
0b
Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hard wired to 0.
Reserved
66-/60-MHz Capability (CAP66)
Not Applicable or Implemented. Hard wired to 0.
Capabilities List (CAPL)
Indicates that a capabilities list is present. Hard wired to 1.
INTA Status (INTAS)
Indicates that an interrupt message is pending internally to
the device. Only PME and Hot Plug sources feed into this
status bit (not PCI INTA-INTD assert and deassert messages).
The INTA Assertion Disable bit, PCICMD1[10], has no effect
on this bit. Note that INTA emulation interrupts received
across the link are not reflected in this bit.
Reserved
(Sheet 2 of 2)
Description
155

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