CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 50

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

50
Bit
6
5
4
3
2
1
0
Access
RW
RO
RO
RO
RO
RO
RO
Default
Value
0b
0b
0b
0b
1b
1b
0b
Parity Error Enable (PERRE)
Controls whether or not the Master Data Parity Error bit in
the PCI Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register
1 = Master Data Parity Error bit in PCI Status register CAN
VGA Palette Snoop Enable (VGASNOOP)
The processor does not implement this bit and it is hard
wired to a 0. Writes to this bit position have no effect.
Memory Write and Invalidate Enable (MWIE)
The processor will never issue memory write and invalidate
commands. This bit is therefore hard wired to 0. Writes to
this bit position will have no effect.
Special Cycle Enable (SCE)
The processor does not implement this bit and it is hard
wired to a 0. Writes to this bit position have no effect.
Bus Master Enable (BME)
The processor is always enabled as a master on the
backbone. This bit is hard wired to a “1”. Writes to this bit
position have no effect.
Memory Access Enable (MAE)
The processor always allows access to main memory,
except when such access would violate security principles.
Such exceptions are outside the scope of PCI control. This
bit is not implemented and is hard wired to 1. Writes to this
bit position have no effect.
I/O Access Enable (IOAE)
This bit is not implemented in the processor and is hard
wired to a 0. Writes to this bit position have no effect.
Encoding
(Sheet 2 of 2)
cannot be set.
be set.
0b
1b
Master Data Parity Error
cannot be set
Master Data Parity Error can be
set
Processor Configuration Registers
Description
Description
Datasheet