CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 248

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.16.34
248
SWSMI - Software SMI
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
As long as there is the potential that DVO port legacy drivers exist which expect this
register at this address, Dev2F0address E0h-E1h must be reserved for this register.
15:8
1:0
Bit
7:1
Bit
0
Access
Access
RW
RW
RW
RW
Default
Default
Value
Value
00h
00h
00b
0b
Software Scratch Bits (SWSB)
Software Flag (SWF)
Used to indicate caller and SMI function desired, as well as
return result.
Processor Software SMI Event (GSSMIE)
When Set this bit will trigger an SMI. Software must write a 0
to clear this bit.
FLR, Core
RST/
PWR
0/2/0/PCI
E0-E1h
0000h
RW
16 bits
Power State (PWRSTAT)
This field indicates the current power state of
the IGD and can be used to set the IGD into a
new power state. If software attempts to write
an unsupported state to this field, write
operation must complete normally on the bus,
but the data is discarded and no state change
occurs. On a transition from D3 to D0 the
graphics controller is optionally reset to initial
values. Behavior of the graphics controller in
supported states is detailed in the power
management section of the Bspec.
Bits[1:0] Power state
00: D0 Default
01: D1 Not Supported
10: D2 Not Supported
11: D3
Description
Processor Configuration Registers
Description
Datasheet