CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 175

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.13.31
Datasheet
MA - Message Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:2
1:0
6:4
3:1
Bit
Bit
0
Access
Access
RW
RW
RO
RW
RO
00000000h
Default
Value
Default
000b
000b
Value
0b
00b
Multiple Message Enable (MME)
System software programs this field to indicate the actual
number of messages allocated to this device. This number is
equal to or less than the number actually requested. The
encoding is the same as for the MMC field below.
Multiple Message Capable (MMC)
System software reads this field to determine the number of
messages being requested by this device. Value:Number of
Messages Requested
000: 1
All of the following are reserved in this implementation: 001:
2
010: 4
011: 8
100: 16
101: 32
110: Reserved
111: Reserved
MSI Enable (MSIEN)
Controls the ability of this device to generate MSIs.
0 = MSI will not be generated.
1 = MSI is generated when we receive PME or HotPlug
Message Address (MA)
Used by system software to assign an MSI address to the
device. The device handles an MSI by writing the padded
contents of the MD register to this address.
Force DWord Align (FDWA)
software are always aligned on a dword address boundary.
hard wired to 0 so that addresses assigned by system
messages. INTA will not be generated and INTA Status
(PCISTS1[3]) will not be set.
0/1/0/PCI
94-97h
00000000h
RO; RW
32 bits
(Sheet 2 of 2)
Description
Description
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